PUBLISHED SILICON

Ultra Low Rdson LDMOS with 12V BVdss

ISCE - August 2022

First-ever LDMOS with Retrograde Body - also in 110nm BCD on SOI

Rsp = 0.84 mOhm.mm2 for 12V breakdown

Reference

Addressing the Challenges of sub-50nm channel LDMOS

ISPSD - June 2021

Silicon confirms the Hybrid Source is the smallest possible source region

at any BCD node to minimize Rsp and cost.

==> Scales with "contact spacing rules"

Reference

No-Snapback LDMOS using Adaptive RESURF & Hybrid Source for Ideal SOA

IEEE JEDS - September 2021

Silicon confirms the transparent process simplicity - no N+ source implant

Enhance SOA (100ns TLP) over full voltage range (12V - 125V rated)

Fast Transient immunity confirmed with 2.5ns TLP

Reference

Hybrid Source LDMOS Drain Engineering for ESD Robustness

IEEE EDL - November 2023

Leveraging the enhanced SOA (no snapback) and power-to-failure (Fast Transient immunity) benefits to optimize drain engineering for BV = 125V.

+68% increase without compromising device characteristics

Enhanced ESD robustness confirmed with 2.5ns TLP

Reference

Enhancing Power MOSFETS - Especially at 90/65/28nm

Find out more

Business photo created by photoangel - www.freepik.com

This website uses cookies.

We use cookies to analyze website traffic and optimize your website experience. By accepting our use of cookies, your data will be aggregated with all other user data.