The heart of the Silicet innovation is the Hybrid Contact, which forms the source of PowerMOS devices instead of the traditional n+ source, without compromising device operating characteristics. Building on the idea of making the metal contact the LDMOS source, one shallow implant is utilized to form two regions - an interfacial dopant segregation layer and a region under the spacer, resulting in three electric junctions - a vertical rectifying barrier junction formed between the metal source contact and the body, a lateral ohmic connection under the spacer, and a PN junction to the channel region under the gate.
The benefits of this innovation: Silicet's source significantly reduces the gain of the lateral parasitic bipolar, which enhances the electrical SOA, improves ESD robustness, and prevents snapback. Using dopant segregation, the barrier height of the Schottky junction is tuned to bring Vth, Idlin and Ioff to appropriate specifications, while utilizing the existing contact silicide formation process flow.
Moving to the self-aligned body LDMOS device, there is excellent synergy with the Hybrid Contact, since the Hybrid Contact implant can be performed at the same mask & process step as the tilted, body implant – leading to an elegant, cost-effective process flow. Since the Silicet source mitigates the lateral parasitic bipolar, there is no need for a “buried body” structure –
saving a mask and process step and avoiding the associated process complications.
The goal of the self-aligned body approach is to reduce the channel length and overall device pitch – minimizing drain-to-source on-resistance (Rdson). However, such self-aligned body devices have intrinsic weaknesses that include a propensity for punch-through, higher leakage, and a limited safe operating area (SOA). These devices also have lithographic limitations and lithographic sensitivity which complicate the manufacturing process. A SASS device mitigates punch through of these shallow body architectures while improving ESD robustness.
The small radius of any self-aligned body under the gate creates dense electric fields, leading to higher leakage and lower breakdown. Placing a retrograde body well under the body is a further enhancement of the SASS device. This does not compromise Rdson or forward device operation, enabling this class of LDMOS device to operate in bias regions traditionally inaccessible – using a simple & cost-effective process flow.
Combining the “power-at-failure” attribute of the SASS device and high e-field mitigation of the retrograde body with an adaptive drain region, enables a SASS-Retro device to provide solutions not previously available to LDMOS designers. A new class of optimization is now possible: ultra-short channel length under large drain currents without snapback.
LDMOS transistors using a self-aligned body to produce sub-50 nm channel lengths for the reduction of on-state resistance and device size have been described. The challenges associated with these structures include both lateral and vertical punch-through, and reduced safe-operating-area (SOA). A novel, ultra-shallow hybrid source combined with a retrograde body region have been shown to be an effective and easily integrated solution to these challenges.