Lowest Rsp & Cost for a given BV
+ Scalable source region follows Contact Spacing Rules
+ Retrograde Body modulates Source E-field and
* New Tradeoff for BV versus Drift Length
* Significantly Improves HCI
+ Optimize Self-Aligned Body
+ Mitigate parasitic NPN - Enhance SOA & EOS-ESD
"Drops-In" to your LDMOS Know-How
Realize HYBRID CONTACT from existing Metal Contact
Seamless Process Integration - at any BCD node!
Poly-to-Poly length scales with Contact Spacing Rules
Hybrid Source & tilted body implants at same mask/process step
==> Lowest Rdson and Device Area for a given BV
NOT REQUIRED: Buried Body or N+ Source implants
Device Overview
Hybrid Contact
The existing metal contact forms the Source of the LDMOS device,
instead of the traditional N+ source, without compromising device operating characteristics.
ONE shallow implant into TWO regions, forms THREE electric junctions :
- Vertical Schottky between the metal source contact and the body,
- Lateral ohmic connection under the spacer, and
- PN junction to the channel region.
BENEFITS : Mitigates lateral parasitic NPN bipolar (removes the N-source)
==> Enhances SOA & ESD robustness, provides Fast-Transient EOS Immunity
Measured silicon: 5V to 100V rated operation
Three Electrical Junctions from One Shallow Implant
==> enables Source Region to follow Contact Spacing Rules
HYBRID SOURCE = Self-Aligned Body + Hybrid CONTACT
Hybrid Contact
Avoids Punch Through
Avoids Punch Through
Suppress parasitic NPN to Enhance SOA
Gate-Aligned implant = Easy Insertion
without compromising device characteristics
Avoids Punch Through
Avoids Punch Through
Avoids Punch Through
Self-Aligned Body is more susceptible to punch through than conventional LDMOS.
==> Lower sub-Vt leak for given Body Doping
ISPSD 2021
Seamless Integration
Avoids Punch Through
Seamless Integration
Shallow Implant Performed after Gate Formation
==> BJT gain reduced by 10E7
==> Insensitive to Dose/Energy
I-V over Temp
Fast-Transient EOS
Seamless Integration
Excellent Operation over Temperature
==> Boost Vth by 250 - 300mV
Fast-Transient EOS
Fast-Transient EOS
Fast-Transient EOS
Hybrid Contact survives to It2
Current (Id) is 10X over PN grounded gate
==> Drain Eng is LIMITING factor
JEDS'21 and EDL'22
COMBINE hybrid source with retrograde body
Insert Retrograde Body
Modulate Source E-Field
Modulate Source E-Field
Non-continuous with body
==> Extend under poly to enhance channel
No surface doping to degrade Vt, Rsp, Idlin
Modulate Source E-Field
Modulate Source E-Field
Modulate Source E-Field
Overcomes small-radius corner of SAB
==> Enables lower leakage & higher BV
** New HCI tradeoff **
ISPSD'21 - Fig 12
Boost Breakdown Voltage
Modulate Source E-Field
Boost Breakdown Voltage
Enables higher drift region dose
==> Minimize Rsp for a given BV
ISPSD'21 - Fig 13
Excellent I-V curves
No Mask Sensitivities
Boost Breakdown Voltage
No impact on device operation
ISCE'22 - Fig 9
No Buried Body
No Mask Sensitivities
No Mask Sensitivities
No Snapback - 100ns TLP
ISPSD'21 - Fig 9
No Mask Sensitivities
No Mask Sensitivities
No Mask Sensitivities
Mask variations don't impact channel parameters
==> Optimize Rsp
ISPSD21 - Fig 14
Contact Us for Detailed Silicon Results
LDMOS transistors using a self-aligned body to produce sub-50 nm channel lengths for the reduction of on-state resistance and device size have been described. The challenges associated with these structures include both lateral and vertical punch-through, and reduced safe-operating-area (SOA). A novel, ultra-shallow hybrid source combined with a retrograde body region have been shown to be an effective and easily integrated solution to these challenges.
